The present invention relates to a transmitting means for transmitting an output signal, a receiving means for receiving an output signal, and methods for transmitting or receiving an output signal. The present invention also relates to highly parallel signal processing in filters for forward error correction (FEC), filters with infinite impulse response (IIR), in particular Tomlinson-Harashima precoding (THP) filters, and filters with finite impulse response (FIR) filters for multi-gigabit data transfer.
A serial baseband data transfer with a high throughput (in the multi-gigabit range), involves compensating for attenuation in the channel even when using a higher-order modulation method. The compensation filters are digitally implemented due to the higher linearity requirement (compared to binary modulation). Data processing in digital compensation filters is often parallelized for systems with multi-gigabit throughput since even modern CMOS processes (CMOS=Complementary Metal Oxide Semiconductor) are limited with regard to the maximum possible clock rates.
In general, FIR filters and IIR filters can be used to compensate for the transfer function. A Tomlinson-Harashima precoder, THP, is a particular form of the IIR filter.
To improve the bit error rate, block encoding is usually used in the form of forward error correction (FEC). Since a redundancy (parity bits) allocated to specific data is encoded in such methods, the data is decoded in the respective same block. This may involve a cyclic insertion of a known marker sequence, a so-called framing of the data, and a synchronization of the frame starts for processing.
Such high-bitrate serial links are also used in the multiplex operation for different data streams. For example, different buses, protocols and/or users are accumulated and separated again. Also, various data sources may be transmitted or received, e.g., to the network node, by a local connection of other networks and local data sinks/sources via the link.
A known solution for the present problem is illustrated in FIG. 8. Data 1002 from possibly different sources 1004 (data source DQ1, DQ2, . . . , DQn) is combined with a multiplexer 1006 into a serial data stream. In this case, the multiplexer can bring blocks of different sizes from different sources into any order. This serial data stream then passes through signal processing on the transmitting means side including a FEC 1008 and a predistortion by means of a THP filter 1012. Then, the data stream is transferred, i.e., the following occurs: a digital/analog (D/A) conversion 1014, a transfer via a medium 1016, an analog/digital (A/D) conversion 1018 and an optional amplification of the analog or digital signal. On the receiving means side, the signal passes through signal processing in the same or equivalent sequence. This includes a channel equalization (feedforward equalizer, FFE) by means of a FIR filter 1022 and a FEC 1024 on a decoder side (Dec). Thereafter, the data is re-divided by a demultiplexer 1026 and forwarded to various data sinks 1028 (DS1, DS2, . . . , DSn).
In order to increase throughput rates, a continuous parallelization of THP filters in conjunction with a decreasing efficiency at an increasing parallelization is known. A THP/IIR filter structure can be transformed such that feedback paths of the IIR filters are eliminated without or with a low delay. Due to the longer feedback paths, known pipelining strategies can be employed, which for a moderate increase in the achievable clock rates for IIR/THP filters. These methods remain limited due to the achievable clock rates in CMOS processes. For FIR filters, the methods Overlap-Save and Overlap-Add are known in order to increase clock rates.